On-SOI integrated circuit comprising a subjacent protection transistor

US9337302B2 · kind B2 · utility

Assignees

• COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR
• STMicroelectronics SA

Inventors

• Claire Fenouillet-Beranger · Grenoble, FR
• Pascal Fonteneau · Theys, FR

Key dates

• Filing date: Jul 2, 2013
• Grant date: May 10, 2016
• Expiry date: Apr 17, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D88/00

Abstract

An integrated circuit features a FET, an UTBOX layer plumb with the FET, an underlayer ground plane with first doping plumb with the FET's gate and channel, first and second underlayer semiconducting elements, both plumb with the drain or source, electrodes in contact respectively with the ground plane and with the first element, one having first doping and being connected to a first voltage, the other having the first doping and connected to a second bias voltage different from the first, a semiconducting well having the second doping and plumb with the first ground plane and both elements, a first trench isolating the first FET from other components of the integrated circuit and extending through the layer into the well, and second and third trenches isolating the FET from the electrodes, and extending to a depth less than a plane/well interface.