Method of fabrication and device configuration of asymmetrical DMOSFET with schottky barrier source
US9337329B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2011 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Jul 6, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source and that may include a PtSi, ErSi layer and may further be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.