Patent · US Active

Memory channel that supports near memory and far memory access

US9342453B2 · kind B2 · utility

77Cited by

34References

16Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Bill Nale · Livermore, US
Raj K. Ramanujan · Federal Way, US
Muthukumar P. Swaminathan · Folsom, US
Tessil Thomas · Bengaluru, IN
Taarinya Polepeddi · London, GB

Key dates

Filing date	Sep 30, 2011
Grant date	May 17, 2016
Priority date	—
Expiry date	May 10, 2032

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.