Semiconductor memory device and methods of operating the same
US9343161B2 · kind B2 · utility
1Cited by
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7Claims
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Key dates
| Filing date | Oct 17, 2014 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | Oct 17, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device comprises a memory cell array including a plurality of memory blocks each including a plurality of pages, wherein each of the plurality of pages includes at least one flag cell indicating whether data is in a corresponding page, and a peripheral circuit configured to read data of flag cells of a selected memory block in response to an erase request and to omit an erase operation on the selected memory block based on the data of the flag cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.