Patent · US Active

Stack packages and methods of manufacturing the same

US9343439B2 · kind B2 · utility

0Cited by
0References
9Claims
0Family size

Assignee

Inventors

Key dates

Filing dateOct 16, 2015
Grant dateMay 17, 2016
Priority date—
Expiry dateOct 16, 2035

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/181
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A stack package includes a substrate having connection terminals and a first chip on the substrate. The first chip has first connectors on edges thereof. A second chip is stacked on the first chip to expose outer portions of the first connectors. The second chip has second connectors on edges thereof. Connection members to connect the exposed outer portions of the first connectors to the connection terminals. Sidewall interconnectors to connect the exposed outer portions of the first connectors to the second connectors. The sidewall interconnectors extend from the exposed outer portions of the first connectors along sidewalls of the second chip to cover the second connectors.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.