Transistors with a gate insulation layer having a channel depleting interfacial charge
US9343540B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2014 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | Aug 14, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
Abstract
A metal-insulator-semiconductor field-effect transistor (MISFET) includes a SiC layer with source and drain regions of a first conductivity type spaced apart therein. A first gate insulation layer is on the SiC layer and has a net charge along an interface with the SiC layer that is the same polarity as majority carriers of the source region. A gate contact is on the first gate insulation layer over a channel region of the SiC layer between the source and drain regions. The net charge along the interface between the first gate insulation layer and the SiC layer may deplete majority carriers from an adjacent portion of the channel region between the source and drain regions in the SiC layer, which may increase the threshold voltage of the MISFET and/or increase the electron mobility therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.