Method for fabricating a recessed channel access transistor device
US9343547B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2015 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | Feb 9, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A trench extends from a main surface of a semiconductor substrate to a predetermined depth. A gate oxide layer is formed in the trench. A buried gate electrode is formed at a lower portion of the trench. The buried gate electrode is capped with a dielectric layer. A pad layer and hard mask layer are formed on the semiconductor substrate. A recess through the pad layer and hard mask layer and into the semiconductor substrate is formed on one side of the trench. A portion of the dielectric layer is revealed within the recess. The hard mask layer is then removed. An ion implantation process is performed to implant dopants on both sides of the trench, thereby forming a source doping region and a drain doping region. The source doping region has a junction depth that is deeper than that of the drain doping region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.