Circuits having programmable impedance elements and vertical access devices
US9343667B1 · kind B1 · utility
2Cited by
5References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 31, 2014 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | Aug 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C14/009
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device can include at least one programmable impedance cell having at least one programmable layer formed between a first terminal and a second terminal, the programmable layer being programmable between at least two impedance states by application of electric fields; and at least a first access bipolar junction transistor (BJT) coupled to the programmable impedance cell having at least a portion formed by a semiconductor material; wherein a base region and a first emitter region or collector region of the first access BJT are vertically aligned with one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.