Erase techniques and circuits therefor for non-volatile memory devices
US9349480B2 · kind B2 · utility
1Cited by
2References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 27, 2014 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Mar 27, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a method that comprises applying a first voltage to a memory cell, applying again the first voltage to the memory cell when the memory cell have not been shifted to an erased condition, and applying a second voltage to the memory cell when the memory cell have not still been shifted to an erased condition, the second voltage being higher than the first voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.