Semiconductor memory apparatus
US9349488B2 · kind B2 · utility
2Cited by
9References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2014 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Sep 25, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory apparatus includes a plurality of data storage regions; a first internal circuit configured to input a plurality of control signals to the plurality of data storage regions; and a second internal circuit configured to control input timing of a test control signal, and input the test control signal to the plurality of data storage regions according to the controlled input timing in response to a test mode signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.