Isolation for embedded devices
US9349654B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2014 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Jul 30, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Device and a method of forming a device are presented. The method includes providing a substrate prepared with isolation regions. The substrate includes first, second and third regions. The first region includes a memory region, the second region includes a high voltage (HV) region and the third region includes a logic region. An additional dielectric layer covering the substrate and the isolation regions is formed. A first select region is selectively processed while protecting first non-select regions. The first select region is one of the first, second and third device regions. A first gate dielectric is formed on the select region. Top substrate active area and isolation regions of the first non-select regions are not exposed during processing of the first select region and forming the first gate dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.