Semiconductor structure and a fabricating method thereof
US9349815B2 · kind B2 · utility
2Cited by
4References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2014 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Sep 18, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate structure is provided. The gate structure includes a substrate, a gate disposed on the substrate and a gate dielectric layer disposed between the substrate and the gate, wherein the gate dielectric layer is in the shape of a barbell. The barbell has a thin center connecting to two bulging ends. Part of the bulging ends extends into the gate and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.