Methods of scaling thickness of a gate dielectric structure, methods of forming an integrated circuit, and integrated circuits
US9349823B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 14, 2013 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Jan 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate, methods of forming an integrated circuit, and integrated circuits are provided. A method of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate includes providing the semiconductor substrate. An interfacial oxide layer is formed in or on the semiconductor substrate. A high-k dielectric layer is formed over the interfacial oxide layer. An oxygen reservoir is formed over at least a portion of the high-k dielectric layer. A sealant layer is formed over the oxygen reservoir. The semiconductor substrate including the oxygen reservoir disposed thereon is annealed to diffuse oxygen through the high-k dielectric layer and the interfacial oxide layer from the oxygen reservoir. Annealing extends the interfacial oxide layer into the semiconductor substrate at portions of the semiconductor substrate that underlie the oxygen reservoir to form a regrown interfacial region in or on the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.