Output circuit for implementing high speed data transmition
US9355706B2 · kind B2 · utility
0Cited by
7References
20Claims
0Family size
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Key dates
| Filing date | Jul 2, 2014 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Jul 24, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An output circuit includes first and second output drivers. The first output driver is configured to transfer a first data signal directly to an output pad in synchronization with a clock signal. The second output driver is configured to transfer a second data signal directly to the output pad in synchronization with an inversion clock signal. The clock signal and the inversion clock enable multiplexing of the first data signal and the second data signal to provide a multiplexed output data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.