Metallization scheme for integrated circuit
US9355718B2 · kind B2 · utility
18Cited by
7References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2015 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Apr 17, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
For multi-level interconnect metallization, each metal level maintains a parallel line arrangement within a region, and the lines of each adjacent metal level are orthogonal or otherwise cross with one another. Vertical shunting among levels for routing in different directions employs short paddles that stay within the parallel scheme, and multiple paddles within a region at the same metal level can be co-linear. Parallel lines in the same metal level can be rotated with respect to one another in adjacent regions, for example to better interface with driver circuitry with orthogonal orientations in the different regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.