Memory array test logic
US9355743B2 · kind B2 · utility
5Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2014 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | May 23, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test circuit for a static random access memory (SRAM) array includes a plurality of stages coupled in a ring. Each stage includes a plurality of bit cells to store information, a bit line and a complementary bit line coupled to the plurality of bit cells, and a plurality of word lines coupled to the plurality of bit cells. Subsets of the plurality of word lines of each of the plurality of stages are selectively enabled based on signals asserted on the complementary bit line of another one of the plurality of stages. The test circuit also includes inversion logic deployed between two of the plurality of stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.