Package on package (PoP) integrated device comprising a plurality of solder resist layers
US9355898B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2014 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Jul 30, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some features pertain to an integrated device that includes a first substrate, a first solder resist layer coupled to the first substrate, a second solder resist layer coupled to the first solder resist layer, and an opening in the first and second solder resist layers, the opening comprising a sidewall completely covered with the second solder resist layer, where a sidewall of the second solder resist layer covers a sidewall of the first solder resist layer. In some implementations, the opening is at least partially filled with an electrically conductive material. The electrically conductive material includes one of solder and/or an interconnect. The integrated device includes a first interconnect coupled to the electrically conductive material. The first interconnect is one of at least a solder, and/or an interconnect ball. In some implementations, the integrated device includes a pad coupled to the substrate, and a first interconnect coupled to the pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.