Methods and structure for carrier-less thin wafer handling
US9355905B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2015 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | May 27, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12042
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming a microelectronic assembly and the resulting structures and devices are disclosed herein. In one embodiment, a method of forming a microelectronic assembly includes removing material exposed at portions of a surface of a substrate to form a processed substrate having a plurality of thinned portions separated by integral supporting portions of the processed substrate having a thickness greater than a thickness of the thinned portions, at least some of the thinned portions including a plurality of electrically conductive interconnects extending in a direction of the thicknesses of the thinned portions and exposed at the surface; and removing the supporting portions of the substrate to sever the substrate into a plurality of individual thinned portions, at least some individual thinned portions including the interconnects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.