Flattened substrate surface for substrate bonding
US9355936B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2014 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Apr 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15788
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.