Chip package having terminal pads of different form factors

US9362187B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventor

• Peter Ossimitz · Munich, DE

Key dates

• Filing date: Jan 18, 2013
• Grant date: Jun 7, 2016
• Expiry date: Apr 11, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2224/73265
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A chip package includes an integrated circuit chip. A first group of terminal pads of the chip package is electrically connected to the integrated circuit chip and a second group of terminal pads of the chip package is electrically connected to the integrated circuit chip. The first and second groups of terminal pads are arranged on a common terminal surface of the chip package. A pad size of a terminal pad of the first group of terminal pads is greater than a pad size of a terminal pad of the second group of terminal pads.