Transaction check instruction for memory transactions
US9367264B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2013 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Jul 10, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing unit of a data processing system having a shared memory system executes a memory transaction including a transactional store instruction that causes a processing unit of the data processing system to make a conditional update to a target memory block of the shared memory system conditioned on successful commitment of the memory transaction. The memory transaction further includes a transaction check instruction. In response to executing the transaction check instruction, the processing unit determines, prior to conclusion of the memory transaction, whether the target memory block of the shared memory system was modified after the conditional update caused by execution of the transactional store instruction. In response to determining that the target memory block has been modified, a condition register within the processing unit is set to indicate a conflict for the memory transaction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.