Circuits and methods for placing programmable impedance memory elements in high impedance states
US9368198B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2014 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Jun 22, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0073
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device can include a plurality of two terminal conductive bridging random access memory (CBRAM) type memory elements; at least one program transistor configured to enable a program current to flow through at least one memory element in response to the application of a program signal at its control terminal and a program bias voltage to the memory element; and an erase load circuit that includes at least one two-terminal diode-like load element, the erase load circuit configured to enable an erase current to flow through the load element and at least one memory element in a direction opposite to that of the program current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.