Capacitor arrangements using a resistive switching memory cell structure

US9368206B1 · kind B1 · utility

Assignee

• Adesto Technologies Corporation · US

Inventors

• John Dinh · Dublin, US
• Ming Sang Kwan · San Leandro, US
• Venkatesh P. Gopinath · Planada, US
• Derric Lewis · Sunnyvale, US
• Shane Hollmer · Grass Valley, US
• John Ross Jameson · Burlingame, US
• Michael Van Buskirk · Saratoga, US

Key dates

• Filing date: Jul 7, 2014
• Grant date: Jun 14, 2016
• Expiry date: Sep 4, 2034

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2213/78
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

In one embodiment, a capacitive circuit can include: (i) a resistive storage element having a solid electrolyte, a first electrode coupled to a first side of the solid electrolyte, and a second electrode coupled to a second side of the solid electrolyte; (ii) the resistive storage element being configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction to form a conductive path between the first and second electrodes, and being configured to be erased to a high resistance state by application of an erase voltage in a reverse bias direction to substantially dissolve the conductive path; and (iii) a first capacitor having the first electrode coupled to a first side of a first oxide layer, and a third electrode coupled to a second side of the first oxide layer.