Method for biasing an embedded source plane of a non-volatile memory having vertical select gates
US9368215B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2015 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Jul 27, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method controls a memory that includes twin memory cells formed in a semiconductor substrate. Each memory cell includes a floating-gate transistor including a state control gate, in series with a select transistor that includes a vertical select control gate, common to the twin memory cells, and a source connected to an embedded source line, common to the memory cells. The drains of the floating-gate transistors of the twin memory cells are connected to a same bit line. The method includes controlling a memory cell so as to turn it on to couple the source line to a bit line coupled to the ground, during a step of programming or reading another memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.