Bit line pre-charge with current reduction
US9368222B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2014 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Oct 1, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are techniques for pre-charging channels when programming memory cells. A pre-charge voltage is applied to both selected bit lines and inhibited bit lines during a channel pre-charge phase. The pre-charge voltage is passed to the channels of NAND strings. The voltage on the inhibited bit lines is then reduced to a program inhibit voltage. Also, the voltage on the selected bit lines is reduced to a program enable voltage. Further, the pre-charge voltage from the channels of the selected NAND strings is discharged while maintaining the pre-charge voltage in the channels of the inhibited NAND strings. The potential in the channels of the inhibited NAND strings may then be boosted and a programming voltage may be applied to a selected word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.