Dielectric wafer level bonding with conductive feed-throughs for electrical connection and thermal management
US9368428B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2007 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Sep 19, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/8585
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating semiconductor and electronic devices at the wafer level is described. In this method, dielectric material is used to wafer bond a device wafer to a submount wafer, after which vias can be structured into the submount wafer and dielectric bonding material to access contact pads on the bonded surface of the device wafer. The vias may subsequently be filled with electrically and thermally conducting material to provide electrical contacts to the device and improve the thermal properties of the finished device, respectively. The post-bonding process described provides a method for fabricating a variety of electronic and semiconductor devices, particularly light emitting diodes with electrical contacts at the bottom of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.