Ashay Chitnis
22Patents
9h-index
18Co-inventors
68Inventor score
Filing activity: Oct 20, 2006 → Jul 3, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7982363B2 | Bulk acoustic device and method for fabricating | Emerging Cross-Sectional Technologies | 94 | Active |
| US9024349B2 | Wafer level phosphor coating method and devices fabricated utilizing method | Electricity | 65 | Active |
| US9159888B2 | Wafer level phosphor coating method and devices fabricated utilizing method | Electricity | 58 | Active |
| US8021904B2 | Ohmic contacts to nitrogen polarity GaN | Electricity | 52 | Active |
| USD582865S1 | LED chip | General | 49 | Expired |
| USD582866S1 | LED chip | General | 36 | Expired |
| USD593968S1 | LED chip | General | 36 | Expired |
| USD602450S1 | LED chip | General | 19 | Expired |
| USD583338S1 | LED chip | General | 10 | Expired |
| US9634191B2 | Wire bond free wafer level LED | Electricity | 8 | Active |
| US8877524B2 | Emission tuning methods and devices fabricated utilizing methods | Emerging Cross-Sectional Technologies | 5 | Active |
| US9496349B2 | P-doping of group-III-nitride buffer layer structure on a heterosubstrate | Electricity | 5 | Active |
| USD616839S1 | LED chip | General | 5 | Expired |
| US8878219B2 | Flip-chip phosphor coating method and devices fabricated utilizing method | Electricity | 4 | Active |
| US9368428B2 | Dielectric wafer level bonding with conductive feed-throughs for electrical connection and thermal management | Electricity | 2 | Active |
| US9196799B2 | LED chips having fluorescent substrates with microholes and methods for fabricating | Electricity | 1 | Active |
| US10199360B2 | Wire bond free wafer level LED | Electricity | 0 | Active |
| US10026814B2 | P-doping of group-III-nitride buffer layer structure on a heterosubstrate | Electricity | 0 | Active |
| US10873002B2 | Permanent wafer bonding using metal alloy preform discs | Electricity | 0 | Active |
| US10211296B2 | P-doping of group-III-nitride buffer layer structure on a heterosubstrate | Electricity | 0 | Active |
| US8617997B2 | Selective wet etching of gold-tin based solder | Electricity | 0 | Active |
| US9786744B2 | P-doping of group-III-nitride buffer layer structure on a heterosubstrate | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.