Method for forming oxide below control gate in vertical channel thin film transistor
US9368601B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2014 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Apr 13, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/40
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fabrication process for a vertical channel transistor provides a desired control gate-to-drain overlap and sufficient isolation between the control gate and an underlying metal line. A body of the transistor is formed on a metal line, such as in a pillar shape. The metal line is oxidized to form metal oxide regions having an expanded volume. A gate insulator material and a control gate material are then deposited. The resulting structure is etched to form separate control gates for each transistor, and to expose the metal oxide. A further etch is performed to remove the metal oxide, forming voids under and around the control gates. An insulation fills the voids. An example implementation is a vertical bit line memory device in which the transistors connect a vertical bit line to a horizontal bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.