Heterojunction bipolar transistor with improved performance and breakdown voltage
US9368608B1 · kind B1 · utility
20Cited by
11References
20Claims
0Family size
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Key dates
| Filing date | Jun 25, 2015 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Jun 25, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Fabrication methods for a device structure and device structures. A trench isolation region is formed that bounds an active device region of a semiconductor substrate. A first semiconductor layer is formed on the active device region and on the trench isolation region. A first airgap is formed between the first semiconductor layer and the active device region. A second airgap is formed between the first semiconductor layer and the trench isolation region. The first airgap extends into the active device region such that the height of the first airgap is greater than the height of the second airgap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.