Integrated circuit comprising a MOS transistor having a sigmoid response and corresponding method of fabrication
US9368611B2 · kind B2 · utility
1Cited by
2References
9Claims
0Family size
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Key dates
| Filing date | Mar 29, 2013 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Apr 8, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
Abstract
An integrated circuit may include at least one MOS transistor having a sigmoid response. The at least one MOS transistor may include a substrate, a source region, a drain region, a gate region, and insulating spacer regions on either side of the gate region. The substrate may include a first region situated under the gate region between the insulating spacer regions. At least one of the source and drain regions may be separated from the first region of the substrate by a second region of the substrate situated under an insulating spacer region, which may be of a same type of conductivity as the first region of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.