Adjustable delay calibration in a critical path monitor
US9369119B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2013 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Feb 26, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/159
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A critical path monitor (CPM) having a set of split paths is configured in an integrated circuit (IC) that includes a corresponding set of critical paths. A first and a second split path is configured with a first and a second simulated delay sections and fine delay sections, respectively. A delay of each of the first and second fine delay sections is adjustable in several steps. The delay of the first fine delay section is adjustable differently from the delay of the second fine delay section in response to a common operating condition change. Differently adjusting the delays of the first and the second fine delay sections causes an edge of a pulse to be synchronized between a first edge detector located after the first simulated delay section and a second edge detector located after the second simulated delay section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.