Wafer test structures and methods of providing wafer test structures
US9372226B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2014 |
| Grant date | Jun 21, 2016 |
| Priority date | — |
| Expiry date | Aug 18, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Wafer test structures and methods of providing wafer test structures are described. The methods include: fabricating multiple test devices and multiple fuse devices on the wafer, each test device having a respective fuse device associated therewith, which open circuits upon failure of the test device; and fabricating a selection circuit operative to selectively connect one test device to a sense contact pad, and the other test devices to a stress contact pad. The selection circuit facilitates sensing one or more electrical signals of the one test device by electrical contact with the sense contact pad, while stress testing the other test devices by electrical contact with the stress contact pad. In one embodiment, each test device has respective first and second switch devices, operative to selectively electrically connect the test device to the sense or stress contact pads. In another embodiment, the method includes wafer testing using the test structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.