Method and system for shutting down active core based caches
US9372803B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2012 |
| Grant date | Jun 21, 2016 |
| Priority date | — |
| Expiry date | Jul 8, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method are presented. Some embodiments include a processing unit, at least one memory coupled to the processing unit, and at least one cache coupled to the processing unit and divided into a series of blocks, wherein at least one of the series of cache blocks includes data identified as being in a modified state. The modified state data is flushed by writing the data to the at least one memory based on a write back policy and the aggressiveness of the policy is based on at least one factor including the number of idle cores, the proximity of the last cache flush, the activity of the thread associated with the data, and which cores are idle and if the idle core is associated with the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.