Mask overlay control
US9377701B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2015 |
| Grant date | Jun 28, 2016 |
| Priority date | — |
| Expiry date | Apr 27, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F9/7069
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
In some embodiments, a mask patterning system includes an electronic memory configured to store an integrated circuit mask layout. A computation tool determines a number of radiation shots to be used to write the integrated circuit mask layout to a physical mask. The computation tool also determines a scaling factor which accounts for expected thermal expansion of the physical mask due to the number of radiation shots used in writing the integrated circuit mask layout to the physical mask. An ebeam or laser writing tool writes the integrated circuit mask layout to the physical mask based on the scaling factor and by using the number of radiation shots.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.