Interconnection for memory electrodes
US9378774B2 · kind B2 · utility
21Cited by
7References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2014 |
| Grant date | Jun 28, 2016 |
| Priority date | — |
| Expiry date | Nov 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/826
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.