Method for planarizing semiconductor device
US9378968B2 · kind B2 · utility
1Cited by
6References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 2, 2014 |
| Grant date | Jun 28, 2016 |
| Priority date | — |
| Expiry date | Sep 2, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76819
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for planarizing a semiconductor device is provided. The method includes steps hereinafter. A substrate is provided with a first dielectric layer covering at least one electrode structure formed thereon. A chemical-mechanical polishing (CMP) process is performed on the first dielectric layer until the at least one electrode structure is exposed. A second dielectric layer is deposited covering the at least one electrode structure and the first dielectric layer. An etching-back process is performed on the second dielectric layer until the at least one electrode structure is exposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.