Patent · US Active

Dual-flag stacked die package

US9379048B2 · kind B2 · utility

1Cited by

2References

17Claims

0Family size

Assignee

SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC · US

Inventors

Frank Tim Jones · Gilbert, US
Phillip Celaya · Gilbert, US

Key dates

Filing date	Feb 28, 2013
Grant date	Jun 28, 2016
Priority date	—
Expiry date	Jun 22, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/181
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

In one embodiment, a semiconductor package includes a first and a second die flag, wherein the first and second die flags are separated by a gap. First and second metal oxide semiconductor field effect transistor (MOSFET) die are on the first and the second die flags, respectively. A power control integrated circuit (IC) is stacked on top of at least one of the first or the second MOSFET die. A mold compound is encapsulating the power control IC, the first and second MOSFET die, and the first and second die flags.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.