Split gate non-volatile flash memory cell having metal gates and method of making same
US9379121B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2015 |
| Grant date | Jun 28, 2016 |
| Priority date | — |
| Expiry date | Jan 5, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory cell includes a substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type spaced apart from the first region, forming a channel region therebetween. A floating gate is disposed over and insulated from a first portion of the channel region which is adjacent the first region. A select gate is disposed over a second portion of the channel region adjacent to the second region, the select gate being formed of a metal material and being insulated from the second portion of the channel region by a layer of silicon dioxide and a layer of high K insulating material. A control gate is disposed over and insulated from the floating gate. An erase gate is disposed over and insulated from the first region, and disposed laterally adjacent to and insulated from the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.