Vertical floating gate NAND with selectively deposited ALD metal films
US9379124B2 · kind B2 · utility
18Cited by
27References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2014 |
| Grant date | Jun 28, 2016 |
| Priority date | — |
| Expiry date | Jun 25, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a monolithic three dimensional NAND string which contains a semiconductor channel and a plurality of control gate electrodes, includes selectively forming a plurality of discrete charge storage regions using atomic layer deposition. The plurality of discrete charge storage regions includes at least one of a metal or an electrically conductive metal oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.