Fet structure for minimum size length/width devices for performance boost and mismatch reduction

US9379186B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Qin Wang · San Jose, US
• Min-hwa Chi · Palo Alto, US
• Meixiong Zhao · Ballston Lake, US
• Zhaoxu Shen · Shanghai, CN
• Haiting Wang · Clifton Park, US
• Lucas M. Salazar · Malta, US
• Lan Yang · Ballston Lake, US

Key dates

• Filing date: Jan 30, 2015
• Grant date: Jun 28, 2016
• Expiry date: Jan 30, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

Methods for preparing CMOS transistors having longer effective gate lengths and the resulting devices are disclosed. Embodiments include forming a dummy gate bound by spacers on opposing sides thereof, on a substrate; removing the dummy gate to form a trench between the spacers; modifying a gate channel portion of the substrate between the spacers to form inner or outer sidewalls; depositing a conformal high-k dielectric layer on the modified gate channel portion; and forming a metal gate in the trench.