Method and apparatus of instruction scheduling using software pipelining
US9383981B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Oct 7, 2014 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Oct 7, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/4452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A modulo scheduling method including calculating at least two candidate initiation intervals between adjacent iterations, searching for schedules of the instructions in parallel by using the candidate initiation intervals, and selecting a schedule determined to be valid from among the searched schedules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.