Semiconductor device and method of forming an embedded SOP fan-out package
US9385006B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2012 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Jul 20, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a ball grid array (BGA) package including first bumps. A first semiconductor die is mounted to the BGA package between the first bumps. The BGA package and first semiconductor die are mounted to a carrier. A first encapsulant is deposited over the carrier and around the BGA package and first semiconductor die. The carrier is removed to expose the first bumps and first semiconductor die. An interconnect structure is electrically connected to the first bumps and first semiconductor die. The BGA package further includes a substrate and a second semiconductor die mounted, and electrically connected, to the substrate. A second encapsulant is deposited over the second semiconductor die and substrate. The first bumps are formed over the substrate opposite the second semiconductor die. A warpage balance layer is formed over the BGA package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.