Stacked semiconductor chips with thermal management
US9385055B2 · kind B2 · utility
9Cited by
5References
17Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Aug 20, 2010 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Sep 25, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of assembling a semiconductor chip device is provided that includes placing an interposer on a first semiconductor chip. The interposer includes a first surface seated on the first semiconductor chip and a second surface adapted to thermally contact a heat spreader. The second surface includes a first aperture. A second semiconductor chip is placed in the first aperture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.