Logical unit address assignment
US9390049B2 · kind B2 · utility
2Cited by
22References
39Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2011 |
| Grant date | Jul 12, 2016 |
| Priority date | — |
| Expiry date | Dec 23, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/883
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described embodiments include logical units within a memory device with control circuitry configured to assign a logical unit address to the logical unit. Apparatus including a plurality of the logical units arranged in a daisy chain configuration and methods of assigning logical unit addresses to the logical units are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.