Sense amplifiers and multiplexed latches
US9390769B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2015 |
| Grant date | Jul 12, 2016 |
| Priority date | — |
| Expiry date | Oct 26, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/037
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multiplexed latches include a multiplexor having a first data input, a second data input, a selection input, and a multiplexor output. A first latch has a first latch clock input, and a first latch output. A second latch has a second latch clock input, and a second latch output. The first latch output is connected to the first data input of the multiplexor, and the second latch output is connected to the second data input of the multiplexor. A feedback loop connects the multiplexor output to the first latch clock input and the second latch clock input. When the selection signal is received by the multiplexor, the feedback loop feeds the output from the multiplexor back to the latches to maintain the existing latch output until the clock signal transitions, to avoid glitches in the multiplexor output when the selection signal and clock signal are not synchronized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.