Semiconductor device and method of forming 3D semiconductor package with semiconductor die stacked over semiconductor wafer
US9391046B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2011 |
| Grant date | Jul 12, 2016 |
| Priority date | — |
| Expiry date | Nov 20, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a substrate and plurality of first semiconductor die having conductive vias formed through the first semiconductor die mounted with an active surface oriented toward the substrate. An interconnect structure, such as bumps or conductive pillars, is formed over the substrate between the first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The second semiconductor die is electrically connected through the interconnect structure to the substrate and through the conductive vias to the first semiconductor die. An underfill material is deposited between the first semiconductor die and substrate. Discrete electronic components can be mounted to the substrate. A heat spreader or shielding layer is mounted over the first and second semiconductor die and substrate. Alternatively, an encapsulant is formed over the die and substrate and conductive vias or bumps are formed in the encapsulant electrically connected to the first die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.