Stacked semiconductor package
US9396765B2 · kind B2 · utility
1Cited by
2References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2014 |
| Grant date | Jul 19, 2016 |
| Priority date | — |
| Expiry date | Oct 16, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A stacked semiconductor package includes a package substrate, an interposer mounted on the package substrate, a plurality of semiconductor chips stacked on the interposer, and a control unit provided in the interposer, that stores in advance data to be written in the plurality of semiconductor chips, and that outputs the data stored in advance according a test mode signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.