Method and apparatus for program and erase of select gate transistors
US9396808B2 · kind B2 · utility
2Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2014 |
| Grant date | Jul 19, 2016 |
| Priority date | — |
| Expiry date | Sep 18, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/611
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are provided for programming select gate transistors in connection with the programming of a set of memory cells. In response to a program command to program memory cells, the select gate transistors are read to determine whether their Vth is below an acceptable range, in which case the select gate transistors are programmed before the memory cells. Or, a decision can be made to program the select gate transistors based on a count of program-erase cycles, whether a specified time period has elapsed and/or a temperature history of the non-volatile storage device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.