Integrated etch/clean for dielectric etch applications

US9396961B2 · kind B2 · utility

Assignee

• Lam Research Corporation · US

Inventors

• Reza Arghavani · Scotts Valley, US
• Shashank Deshmukh · San Jose, US
• Eric A. Hudson · Berkeley, US
• Tom A. Kamp · San Jose, US
• Samantha Tan · Fremont, US
• Gerardo Delgadino · Fremont, US

Key dates

• Filing date: Feb 2, 2015
• Grant date: Jul 19, 2016
• Expiry date: Feb 2, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76897
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The embodiments herein relate to methods and apparatus for etching a recessed feature in dielectric material. In various embodiments, a recessed feature is formed in two etching operations. The first etching operation partially etches the features and may take place in a reactor configured to produce a capacitively coupled plasma. The first etching operation may end before the underlying semiconductor material experiences substantial damage due to penetration of ions through the dielectric atop the semiconductor material. The second etching operation may take place in a reactor configured to produce an inductively coupled plasma. Both the first and second etching operations may themselves be multi-step, cyclic processes.