Method for forming source/drain contacts during CMOS integration using confined epitaxial growth techniques
US9397003B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2015 |
| Grant date | Jul 19, 2016 |
| Priority date | — |
| Expiry date | May 27, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0184
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a first confined raised source/drain region between an adjacent pair of first dummy gate structures and a second confined raised source/drain region between an adjacent pair of second dummy gate structures during a same first epitaxial growth process, the first and second confined raised source/drain regions including a first semiconductor material. Thereafter, a replacement metal gate process is performed to replace the pairs of first and second dummy gate structures with respective pairs of first and second replacement gate structures. After the replacement metal gate process is performed, a first contact element is formed to the first confined raised source/drain region, a second epitaxial growth process is performed to form a layer of a second semiconductor material above the second confined raised source/drain region, and a second contact element is formed to the layer of second semiconductor material layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.